Computationally efficient real-time digital predistortion architectures for envelope tracking power amplifiers

摘要

This paper presents and discusses two possible real-time digital predistortion (DPD) architectures suitable for envelope tracking\ud(ET) power amplifiers (PAs) oriented at a final computationally efficient implementation in a field programmable gate\udarray (FPGA) device. In ET systems, by using a shaping function is possible to modulate the supply voltage according to different\udcriteria. One possibility is to use slower versions of the original RF signal’s envelope in order to relax the slew-rate (SR) and\udbandwidth (BW) requirements of the envelope amplifier (EA) or drain modulator. The nonlinear distortion that arises when\udperforming ET with a supply voltage signal that follows both the original and the slow envelope will be presented, as well as the\udDPD function capable of compensating for these unwanted effects. Finally, two different approaches for efficiently implementing\udthe DPD functions, a polynomial-based and a look-up table-based, will be discussed.